1. Field of the Invention
This invention relates to a fast digital multiplier adapted to multiply two binary numbers together. The invention also relates to digital adder-multipliers which can calculate functions of the kind y.sub.o = A.sub.1.sup.. y.sub.1 + A.sub.2.sup.. y.sub.2 + . . . + A.sub.i.sup.. y.sub.i + . . . + A.sub.n.sup.. y.sub.n, formed by the sum of n products of two numbers A.sub.i and y.sub.i, i being a whole number between 1 and n. The invention also relates to digital filters comprising such adder-multipliers.
2. Description of the Prior Art
The number of digits or bits in a binary number may of course be very considerable and the time taken for a multiplication operation in known multiplier circuits is greater in proportion as the number of digits or bits of the values to be multiplied together is higher. Also, if high accuracy is required the values must have a large number of digits. The known multiplier circuits therefore operate fairly slowly because of the large number of digits in the values.